(1) Field of the Invention
This invention relates to a semiconductor memory and, more particularly, to a nonvolatile semiconductor memory based on a virtual ground method.
(2) Description of the Related Art
In recent years large-capacity and highly-integrated memories have been required. As a result, nonvolatile semiconductor memories based on a multi value method, a virtual ground method, and the like in which effective cell area can be reduced have been developed and put to practical use.
Semiconductor memories based on a virtual ground method have a structure in which two memory cells share one bit line, so high integration levels can be attained.
FIG. 5 is a view showing the rough structure of part of a conventional nonvolatile semiconductor memory based on a virtual ground method.
A semiconductor memory 30 includes a virtual ground line VRG, a sense amplifier 31, a cascode circuit 32, a precharge circuit 33, and a selection circuit 34 and has a structure in which memory cells M1 through M5 are connected in parallel among a plurality of bit lines BL1 through BL6 intersecting a word line WL. A gate in each of the memory cells M1 through M5 is connected to the word line WL. A drain in each of the memory cells M1 through M5 is connected to one of the bit lines BL1 through BL6. A source in each of the memory cells M1 through M5 is also connected to one of the bit lines BL1 through BL6.
Now, operation performed when the memory cell M2 is read will be described.
When the memory cell M2 is read, a voltage of, for example, 5 V is applied first to the word line WL. Then the memory cells M1 through M5 will go into the ON state. Moreover, the virtual ground line VRG is connected by the selection circuit 34 to the bit line BL2 connected to a source s1 of the memory cell M2. The cascode circuit 32 is connected by the selection circuit 34 to the bit line BL3 connected to a drain d1 of the memory cell M2. A voltage of, for example, 1 V is applied to the bit line BL3 connected to the drain d1.
The precharge circuit 33 is connected by the selection circuit 34 to the opposite bit line BL4 connected to the memory cell M3, which is adjacent to the memory cell M2 and which shares the bit line BL3 connected to the drain d1 of the memory cell M2, to charge the bit line BL4 so that its potential will be equal to that of the drain d1 of the memory cell M2. This prevents an electric current Ic which runs through the bit line BL3 from flowing to the memory cell M3 not selected. The bit lines BL1, BL5, and BL6 connected to the memory cells M1, M4, and M5, respectively, are in a floating state, that is to say, they are not connected to power or virtual ground.
When the memory cell M2 is in a write state (PGM state), that is to say, when the memory cell M2 stores “0,” an electric current Ids which flows between the drain d1 and source s1 in the memory cell M2 is not powerful. On the other hand, when the memory cell M2 is in an erase state (ERASE state), that is to say, when the memory cell M2 stores “1,” the electric current Ids is powerful. The cascode circuit 32 converts the electric current Ic which runs through the bit line BL3 to voltage and inputs it to the sense amplifier 31. The sense amplifier 31 is connected to a reference circuit (not shown). The sense amplifier 31 judges by comparing a reference current which flows through the reference circuit and a reference signal input to the sense amplifier 31 whether the memory cell M2 is in a PGM state or in an ERASE state, and outputs the result of judgment as data.
It is assumed that a reference current of 15 μA is passed through the reference circuit (not shown). If the value of the electric current Ic which runs through the bit line BL3 is greater than 15 μA, then the sense amplifier 31 judges that the memory cell M2 is in an ERASE state. If the value of the electric current Ic which runs through the bit line BL3 is smaller than 15 μA, then the sense amplifier 31 judges that the memory cell M2 is in a PGM state.
To prevent an error in judgment, usually some margin will be left. It is assumed that an electric current of 10 μA flows in a PGM state and that an electric current of 20 μA flows in an ERASE state. Moreover, as described above, it is assumed that a reference current of 15 μA is passed through the reference circuit. Then a margin of ±5 μA will be left.
However, the conventional semiconductor memory 30 has the following problems.
FIG. 6 is a view showing the rough structure of part of the semiconductor memory in which a combination of storage states of memory cells is made.
As shown in FIG. 6, operation performed at read time in a case where the memory cell M2 is in a PGM state and where the memory cells M3, M4, and M5 are in an ERASE state will be described first.
When the memory cell M2 is read, it is in a PGM state and an electric current which flows between the drain d1 and source s1 in the memory cell M2 is not powerful. Therefore, the potential of the drain d1 is slightly higher. At this time, the memory cell M3, which is on the drain d1 side and which is adjacent to the memory cell M2, is in an ERASE state. The memory cell M4 next to the memory cell M3 is also in an ERASE state. A powerful electric current flows in an ERASE state. Therefore, the potential of the bit line BL4 connected to the memory cell M3 which is charged so that its potential will be equal to that of the drain d1 is slightly lower. As a result, an electric current Idp will flow from the drain d1 to the memory cell M3. The sense amplifier 31 judges the storage state of the memory cell M2 on the basis of the electric current Ic which runs through the bit line BL3. Therefore, if the electric current Ic which runs through the bit line BL3 for reading is given by Ids+Idp, the value of the electric current Ic appears to be greater than that of the electric current Ids which originally flows between the drain d1 and source s1 in the memory cell M2.
It is assumed that the value of a reference current, which flows through the reference circuit (not shown) and which is used by the sense amplifier 31 for comparison, is 15 μA, that usually the value of Ids is 10 μA in a PGM state and 20 μA in an ERASE state, and that a margin of 5 μA is left in each state. Then Idp will decrease this margin. If Idp exceeds 5 μA, the sense amplifier 31 will judge the memory cell M2 to be in an ERASE state, but in reality it is in a PGM state.
FIG. 7 is a view showing the rough structure of part of the semiconductor memory in which another combination of storage states of memory cells is made.
Now, operation performed at read time in a case where the memory cells M2 and M3 are in an ERASE state and where the memory cells M4 and M5 are in a PGM state will be described.
In this case, the memory cell M2 to be read is in an ERASE state and a powerful electric current flows between the drain d1 and source s1 in the memory cell M2. Therefore, the voltage of the drain d1 is slightly lower. At this time the memory cell M3, which is on the drain d1 side and which is adjacent to the memory cell M2, is in an ERASE state. The memory cell M4 next to the memory cell M3 is in a PGM state. As a result, an electric current which runs through the bit line BL4 is not powerful and the voltage of the bit line BL4 connected to the memory cell M3 is slightly higher. Therefore, the electric current Idp will flow from the bit line BL4 on the memory cell M3 side to the drain d1. The sense amplifier 31 judges the storage state of the memory cell M2 on the basis of the electric current Ic which runs through the bit line BL3. Accordingly, if the electric current Ic which runs through the bit line BL3 for reading is given by Ids−Idp, the value of the electric current Ic appears to be smaller than that of the electric current Ids which originally flows between the drain d1 and source s1 in the memory cell M2.
It is assumed that the value of a reference current, which flows through the reference circuit (not shown) and which is used by the sense amplifier 31 for comparison, is 15 μA, that usually the value of Ids is 10 μA in a PGM state and 20 μA in an ERASE state, and that a margin of 5 μA is left in each state. Then Idp will decrease this margin. If Idp exceeds 5 μA, the sense amplifier 31 will judge the memory cell M2 to be in a PGM state, but in reality it is in an ERASE state.